
#ifndef __AD9171REG_H
#define __AD9171REG_H

#include <stdint.h>


uint32_t ad9171_reset [6] = {
    0x000081, // reset whole chip
    0x00003C, // release reset and set spi to 4 wire mode
    0x009100, // power up clock receiver
    0x020601, // take phy out of reset
    0x070501, // enable boot loader
    0x009000 // Power on DACs and bias circuitr
};

//uint32_t ad9171_cfg_clk [16] = {
uint32_t ad9171_cfg_clk [3] = {
    //0x009500,   //using internal pll
    //0x079000,   //using pll
   // 0x079100,   //using pll
    //0x0796E5,   //DAC PLL required write
    //0x07A0BC,   //DAC PLL required write
    //0x079408,   //set dac pll charge pump current
    //0x079710,   //DAC PLL required write
    //0x079720,   //DAC PLL required write
    //0x079810,   //DAC PLL required write
    //0x07A27F,   //DAC PLL required write
    //0x0799CC,   //DAC N divider is 12
    //0x079318,   //DAC M divider is 1
    //0x009401,   //DAC pll output divider by 2
    //0x079202,   //reset vco
    //0x079200,   //
    //0x87B500    //read reg ensure pll is locked

	    0x009501,   //using internal pll
        0x0790FF,   //using pll
	    0x0791FF  //using pll

};

uint32_t ad9171_cfg_dll [8] = {
    0x00C000,   //Power-up delay line
    0x00DB00,   //
    0x00DB01,   //Update DLL settings to circuitry.
    0x00DB00,   //
    0x00C168,   //set dll search mode
    0x00C169,   //set dll search mode
    0x00C701,   //Enable DLL read status
    0x80C300    //Ensure DLL is locked by reading back a value of 1 for Bit 0 of this register.
};

uint32_t ad9171_cfg_calib [5] = {
    0x00502A,   //Optimized calibration setting register write.
    0x006168,   //Required calibration control register write.
    0x005182,   //Required calibration control register write.
    0x005183,   //Required calibration control register write.
    0x008103,   //Required calibration control register write
};

uint32_t ad9171_cfg_204b [11] = {
    0x010000,   //Power up digital datapath clocks when internal clocks are stable.
    0x030000,   //Keep links disabled until end of routine
    0x011000,   //Set to single link mode
    0x011186,   //48x interp
    0x008400,   //sysref is ac-coupled
    0x031240,   //
	//0x030000,   //Keep links disabled until end of routine
    0x047509,   //
    0x045300,   //disable scrambling and set L = 1
    0x04582F,   //set subclass to 1 and np as 16
    0x045920,   //set using jesd204b and s = 1
    // 0x045A80,   //set HD = 1
    0x047501    //Bring the JESD204B quad-byte deframer out of reset.
};

    // 0x045403,   //set F = 4
    // 0x04551F,   //Set K = 32
    // 0x045601,   //Set M = 2
    // 0x04570F,   //Set N = 16

uint32_t ad9171_cfg_channel_datapath [25] = {
    0x000841,   //CHANNEL_PAGE,select all channel
    0x0146ff,   //CHNL_GAIN[7:0]
    0x014707,   //CHNL_GAIN[7:0]
    0x013008,   //disable nco
    0x013200,   //Set FTW = 0
    0x013300,   //Set FTW = 0
    0x013400,   //Set FTW = 0
    0x013500,   //Set FTW = 0
    0x013600,   //Set FTW = 0
    0x013700,   //Set FTW = 0
    0x013800,   //NCO PHASE = 0
    0x013900,   //NCO PHASE = 0
    0x013A00,   //KEEP 0
    0x013B00,   //KEEP 0
    0x013C00,   //KEEP 0
    0x013D00,   //KEEP 0
    0x013E00,   //KEEP 0
    0x013F00,   //KEEP 0
    0x014000,   //KEEP 0
    0x014100,   //KEEP 0
    0x014200,   //KEEP 0
    0x014300,   //KEEP 0
    0x014400,   //KEEP 0
    0x014500,   //KEEP 0
    0x013101    //Update all NCO phase and FTW words.
};

uint32_t ad9171_cfg_main_datapath [26] = {
//uint32_t ad9171_cfg_main_datapath [23] = {
    0x000841,   //MAINDAC_PAGE.
    //0x011208,   //Disable NCO
	0x01120C,   //Enable NCO , upper sideband
	//0x01120E,   //Enable NCO , lower sideband
//     0x011455,   //Write DDSM_FTW Set NCO to 30MHz
//     0x011555,   //Write DDSM_FTW Set NCO to 30MHz
//     0x011655,   //Write DDSM_FTW Set NCO to 30MHz
//     0x011755,   //Write DDSM_FTW Set NCO to 30MHz
//     0x011855,   //Write DDSM_FTW Set NCO to 30MHz
//     0x011901,   //Write DDSM_FTW Set NCO to 30MHz
    0x01148A,   //Write DDSM_FTW Set NCO to 380MHz
    0x0115E3,   //Write DDSM_FTW Set NCO to 380MHz
    0x011638,   //Write DDSM_FTW Set NCO to 380MHz
    0x01178E,   //Write DDSM_FTW Set NCO to 380MHz
    0x0118E3,   //Write DDSM_FTW Set NCO to 380MHz
    0x011910,   //Write DDSM_FTW Set NCO to 380MHz

    0x0148ff,   //set dc offset
    0x014950,   //set dc offset
    0x01e600,   //select main dac data src
    0x011C00,   //Write DDSM_NCO_PHASE_OFFSET to 0
    0x011D00,   //Write DDSM_NCO_PHASE_OFFSET to 0
    0x012400,   //Write DDSM_ACC_MODULUS to 0
    0x012500,   //Write DDSM_ACC_MODULUS to 0
    0x012600,   //Write DDSM_ACC_MODULUS to 0
    0x012700,   //Write DDSM_ACC_MODULUS to 0
    0x012800,   //Write DDSM_ACC_MODULUS to 0
    0x012900,   //Write DDSM_ACC_MODULUS to 0
    0x012A00,   //Write DDSM_ACC_MODULUS to 0
    0x012B00,   //Write DDSM_ACC_MODULUS to 0
    0x012C00,   //Write DDSM_ACC_MODULUS to 0
    0x012D00,   //Write DDSM_ACC_MODULUS to 0
    0x012E00,   //Write DDSM_ACC_MODULUS to 0
    0x012F00,   //Write DDSM_ACC_MODULUS to 0
    0x011301    //Update all NCO phase and FTW words
};

uint32_t ad9171_cfg_serdes [40] = {
    0x0240AA,   //EQ settings determined by amount of insertion loss according to Table 18. For insertion loss 閿熸枻鎷� 11 dB, set to 0xAA;otherwise, set to 0xFF
    0x0241AA,   //EQ settings determined by amount of insertion loss according to Table 18. For insertion loss 閿熸枻鎷� 11 dB, set to 0xAA;otherwise, set to 0xFF
    0x024255,   //EQ settings determined by amount of insertion loss according to Table 18. For insertion loss 閿熸枻鎷� 11 dB, set to 0xAA;otherwise, set to 0xFF
    0x024355,   //EQ settings determined by amount of insertion loss according to Table 18. For insertion loss 閿熸枻鎷� 11 dB, set to 0xAA;otherwise, set to 0xFF
    0x02441F,   //EQ settings
    0x02451F,   //EQ settings
    0x02461F,   //EQ settings
    0x02471F,   //EQ settings
    0x02481F,   //EQ settings
    0x02491F,   //EQ settings
    0x024A1F,   //EQ settings
    0x024B1F,   //EQ settings
    0x0201FE,   //Power down unused PHYs. Bit x corresponds to SERDINx閿熸枻鎷� pin power-down.
    0x020301,   //power up syncout in single link mode
    0x025301,   //set syncout0 to lvds output
    0x025401,   //set syncout1 to lvds output
    0x021016,   //SERDES required register write
    0x021605,   //SERDES required register write
    0x0212FF,   //SERDES required register write
    0x021200,   //SERDES required register write
    0x021087,   //SERDES required register write
    0x021611,   //SERDES required register write
    0x021301,   //SERDES required register write
    0x021300,   //SERDES required register write.
    0x020000,   //Power up the SERDES circuitry blocks,after configure this register please wait 100ms
    0x021086,   //SERDES required register write
    0x021640,   //SERDES required register write
    0x021301,   //SERDES required register write
    0x021300,   //SERDES required register write
    0x021086,   //SERDES required register write
    0x021600,   //SERDES required register write
    0x021301,   //SERDES required register write
    0x021300,   //SERDES required register write
    0x021087,   //SERDES required register write
    0x021601,   //SERDES required register write
    0x021301,   //SERDES required register write
    0x021300,   //SERDES required register write
    0x028005,   //SERDES required register write
    0x028001,   //Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration
    0x828100    //Ensure Bit 0 of this register reads back 1 to indicate the SERDSES PLL is locked
};

/*
bit 2 1 0
    0 0 0 Data is from SERDIN0閿燂拷.
    0 0 1 Data is from SERDIN1閿燂拷.
    0 1 0 Data is from SERDIN2閿燂拷.
    0 1 1 Data is from SERDIN3閿燂拷.
    1 0 0 Data is from SERDIN4閿燂拷.
    1 0 1 Data is from SERDIN5閿燂拷.
    1 1 0 Data is from SERDIN6閿燂拷.
    1 1 1 Data is from SERDIN7閿燂拷
*/
//as datasheet page 18 shows when pageing link 0, link lanex = logicalLane x
//when pageing link1 (dual link mode only) link lane x = LogicalLane x + 4
uint32_t ad9171_cfg_204b_common [14] = {
    0x030808,   //LogicalLane1 = 1 LogicalLane0 = 0
    0x03091A,   //LogicalLane3 = 3 LogicalLane2 = 2
    0x030A2C,   //LogicalLane5 = 5 LogicalLane4 = 4
    0x030B3E,   //LogicalLane7 = 7 LogicalLane6 = 6

	//0x030810,   //LogicalLane1 = 1 LogicalLane0 = 0
	//0x030932,   //LogicalLane3 = 3 LogicalLane2 = 2
	//0x030A54,   //LogicalLane5 = 5 LogicalLane4 = 4
	//0x030B76,   //LogicalLane7 = 7 LogicalLane6 = 6

    0x03060C,
    0x03070C,
    0x030400,   //set to 0 wait chip cal delay
    0x030500,   //set to 0 wait chip cal delay
    0x003BF1,
    0x003A02,
    0x030001,
    0x01DE03,
    0x0008C0,
    0x05960C
};



#endif
